The Analog to Digital Converter (ADC)
[How it works] [Modes] [Registers] [Hardware Issues]

How it works

The Analog to Digital Converter (ADC) is used to convert an analog voltage (a voltage that vary continuously within a known range) to a 10-bit digital value. For instance, it can be used to log the output of a sensor (temperature, pressure, etc) at regular intervals, or to take some action in function of the measured variable value. There are several types of ADCs. The one used by AVR is of the "succesive approximation ADC" kind. The following is a simplified scheme of the ADC.

At the input of the ADC itself is an analog multiplexer, which is used to select between eight analog inputs. That means that you can convert up to eight signals (not at the same time of course). At the end of the conversion, the correponding value is transferred to the registers ADCH and ADCL. As the AVR's registers are 8-bit wide, the 10-bit value can only be held in two registers.

The analog voltage at the input of the ADC must be greater than 0V, and smaller than the ADC's reference voltage AREF. The reference voltage is an external voltage you must supply at the Aref pin of the chip. The value the voltage at the input is converted to can be calculated with the following formula:

ADC conversion value = round( (vin/vref)*1023)

Since it is a 10-bit ADC, you have 1024(1024=2^10) possible output values (from 0 to 1023). So, if vin is equal to 0V, the result of the conversion will be 0, if vin is equal to vref, it will be 1023, and if vin is equal to vref/2 it will be 512. As you can see, since you are converting a continuous variable (with infinite possible values) to a variable with a finite number of possible values (elegantly called a "discrete variable"), the ADC conversion produces an error, known as "quantization error".

Modes of Operation

The ADC has two fundamental operation modes: Single Conversion and Free Running. In Single Conversion mode, you have to initiate each conversion. When it is done, the result is placed in the ADC Data register pair and no new conversion is started. In Free Runing mode, you start the conversion only once, and then, the ADC automatically will start the following conversion as soon as the previous one is finished.

The analog to digital conversion is not instantaneous, it takes some time. This time depends on the clock signal used by the ADC. The conversion time is proportional to the frequency of the ADC clock signal, which must be between 50kHz and 200kHz.

If you can live with less than 10-bit resolution, you can reduce the conversion time by increasing the ADC clock frequency. The ADC module contains a prescaler, which divides the system clock to an acceptable ADC clock frequency. You configure the division factor of the prescaler using the ADPS bits (see below for the details).

To know the time that a conversion takes, just need to divide the number of ADC clock cycles needed for conversion by the frequency of the ADC clock. Normaly, a conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (by setting the ADEN bit) takes 25 ADC clock cycles. This first conversion is called an "Extended Conversion". For instance, if you are using a 200kHz ADC clock signal, a normal conversion will take 65 microsenconds (13/200e3=65e-6), and an extended conversion will take 125 microseconds (25/200e3=125e-6).

Registers

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
---
---
---
---
---
MUX2
MUX1
MUX0

This register is used to select which of the 8 channel (between ADC0 to ADC7) will be the input to the ADC. Since there are 8 possible inputs, only the 3 least significant bits of this register are used. The following table describe the setting of ADMUX.

MUX2 MUX1 MUX0 Selected Input
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1

You can see that it's possible to load a register with the desired input number and write it to ADMUX directly, as the register does not contain any other flags or setting bits.
If these bits are changed during a conversion, the change will have no effect until this conversion is complete. This is a problem when multiple channels are scanned:

If you can make sure that the ISR always changes the ADMUX value to the next channel (or some other value that can be reconstructed by the next ISR) the value in the ADC data register pair is always the conversion result from the last ADMUX change. When the ISR changes ADMUX from 2 to 3, the value in the data registers is from channel 2.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADEN (ADC Enable) bit : Setting this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion.

ADSC (ADC Start Conversion) bit : In Free Running Mode, you must set this bit to start the first conversion. The following conversions will be started automatically. In Single Conversion Mode, you must set it to start each conversion. This bit will be cleared by hardware when a normal conversion is completed. Remember that the first conversion after the ADC is enabled is an extended conversion. An extended conversion will not clear this bit after completion.

ADFR (ADC Free Running Select) bit : If you want to use the Free Running Mode, you must set this bit.

ADIF (ADC Interrupt Flag) bit : This bit is set when an ADC conversion is completed. If the ADIE bit is set and global interrupts are enabled, the ADC Conversion Complete interrupt is executed. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical 1 (!) to the flag. This has a nasty side effect : if you modify some other bit of ADCSR using the SBI or the CBI instruction, ADIF will be cleared if it has become set before the operation.

ADIE (ADC Interrupt Enable) bit : When the ADIE bit is set and global interrupts are enabled, the ADC interrupt is activated and the ADC interrupt routine is called when a conversion is completed. When cleared, the interrupt is disabled.

ADPS (ADC Prescaler Select ) bits : These bits determine the division factor between the AVR clock frequency and the ADC clock frequency. The following table describe the setting of these bits :

0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128

These registers hold the result of the last ADC conversion. ADCH holds the two most significant bits, and ADCL holds the remaining bits.

Here is a code snippet to make a conversion of ADC3. The result is placed in r16 and r17. The AVR is running at 4MHz:

The ATmega series of AVRs have a more complex ADC. They are similar to the ADC explained here, but have some additional features like (see the datasheet for the details) :

• 7 Differential Input Channels
• 2 Differential Input Channels with Optional Gain of 10x and 200x(1)
• Selectable 2.56V ADC Reference Voltage
• ADC Start Conversion by Auto Triggering on Interrupt Sources

Hardware issues